1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device having a nonvolatile semiconductor memory device.
2. Description of the Related Art
As a nonvolatile semiconductor memory device, for example, an electrically erasable programmable read only memory (EEPROM) which can electrically program and erase data is known. The EEPROM has a memory cell array configured by memory cells arranged at intersections between word lines extending in a row direction and bit lines extending in a column direction to intersect with the word lines. Generally, in each memory cell, for example, a MOS transistor with a stacked gate structure configured by laminating a floating gate and control gate is used. Particularly, a NAND flash memory has a configuration in which a plurality of memory cell transistors are serially connected to form a NAND string and block selection transistors are arranged on both sides of the NAND string. Further, element isolation regions are arranged in parallel with respect to the active areas of the memory cells to form the memory cell array.
Generally, the word line is formed of a laminated film of conductive polysilicon and metal silicide or a laminated film of conductive polysilicon and metal in order to lower the resistance thereof. Such a NAND flash memory is described in Jpn. Pat. Appln. KOKAI Publication No. 2003-7870, for example.
The NAND flash memory is developed to have a larger scale capacity and rapid shrinkage of the memory cell transistor proceeds accordingly. Particularly, a reduction or shrinkage in the channel length and channel width of the memory cell transistor is significant. Even if they are shrunk, it is desired to suppress the resistance of the word line. This is because it is desired to maintain the high-speed operation of the NAND flash memory. As a result, the gate structure of the memory cell transistor or the so-called stacked gate structure tends to become long in the vertical direction. This is called a high aspect ratio stacked gate structure. At present, the aspect ratio of the stacked gate structure ranges from 7 to 7.5.
Thus, in order to enhance the integration density of the memory cell transistors while suppressing an increase in the resistance of the word line, the aspect ratio of the stacked gate structure tends to be made higher. However, in order to attain the high aspect ratio, it becomes difficult to process the stacked gate structure.